Front-rear contacts are commonly provided in several electronic devices, which are integrated in a corresponding chip (so as to electrical contact a front surface of the chip to an opposed rear—or back—surface thereof).
A typical example is that of an electronic device of the Silicon On Insulator (SOI) type. These devices are integrated in a composite wafer, in which a buried insulating layer (such as of silicon oxide) separates two semiconductor layers (such as of mono-crystal silicon). Particularly, the lower (thicker) silicon layer defines a common substrate; the upper (thinner) silicon layer acts as an active layer housing the different electronic components (such as, MOSFET transistors) of the device.
The oxide layer provides a robust voltage insulation of the components in the active layer from the substrate. Moreover, DTI (Deep Trench Isolation) processes may be efficiently employed to provide lateral insulation from adjacent components that are integrated in the same device within different insulated regions of the active layer. In particular, such regions are fully insulated by means of the buried insulating layer and the DTI trenches. In addition, standard LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) processes may be used to provide a further lateral insulation of the components that are integrated in the same insulated region. Moreover, the devices of the SOI type have other important advantages. For example, they often do not suffer leakage effects between adjacent components. Moreover, the parasitic capacitances of the components integrated in the device are significantly reduced.
Usually it is desired to maintain the substrate at a predetermined voltage (for example, to avoid undesired capacitive coupling effects). Particularly, when the substrate is not directly accessible from the rear surface of the device it is typically biased to the desired voltage through a corresponding contact formed on its front surface (defined by the active layer). A typical example is a device that is mounted on a chip carrier with a flip-chip technique, wherein the front surface of the device faces the chip carrier (with its terminals that are directly connected to corresponding bumps of the chip carrier).
For this purpose, a via hole (or simply via) crossing the insulating layer of the device is provided so as to connect the two silicon layers (i.e., the active layer and the substrate). Typically, the via is formed in a dedicated insulated region of the active layer (defined by an insulating trench extending from the front surface to the insulating layer).
In the state of the art such via is obtained by selectively etching the active layer so forming a trench extending from the front surface down to the substrate. The walls of the trench are then covered by a conformal conductive layer (i.e., such as to substantially follow the profile of the underlying structure), which conductive layer further extends on the front surface so as to define the desired front-rear contact.
A drawback of the solution described above is that this trench wastes a significant area of the device. In fact, the trench typically must be wide enough to ensure that the conductive layer uniformly covers all its walls so as to be conformal (i.e., the trench has a significant so-called “step coverage”). This significantly increases the size of the whole device.
Similar considerations apply to (standard) electronic devices, which are formed on a silicon substrate directly (without any insulating layer). In this case as well, the front-rear contact is formed in a dedicated insulated region of the chip (defined by an insulating trench crossing the whole chip from the front surface to the rear surface); two opposed terminals are then arranged on the front surface and on the rear surface of the chip.
As above, the front-rear contact wastes a significant area of the device to achieve the required electrical characteristics (and especially a high conductivity); therefore, this again adversely affects the overall size of the device.